ITM_Type Struct Reference

#include <core_cm3.h>

Data Fields
union {
__O uint8_t   u8
__O uint16_t   u16
__O uint32_t   u32
}	PORT [32]
uint32_t	RESERVED0 [864]
__IO uint32_t	TER
uint32_t	RESERVED1 [15]
__IO uint32_t	TPR
uint32_t	RESERVED2 [15]
__IO uint32_t	TCR
uint32_t	RESERVED3 [29]
__IO uint32_t	IWR
__IO uint32_t	IRR
__IO uint32_t	IMCR
uint32_t	RESERVED4 [43]
__IO uint32_t	LAR
__IO uint32_t	LSR
uint32_t	RESERVED5 [6]
__I uint32_t	PID4
__I uint32_t	PID5
__I uint32_t	PID6
__I uint32_t	PID7
__I uint32_t	PID0
__I uint32_t	PID1
__I uint32_t	PID2
__I uint32_t	PID3
__I uint32_t	CID0
__I uint32_t	CID1
__I uint32_t	CID2
__I uint32_t	CID3

Field Documentation

__I uint32_t ITM_Type::CID0

Offset: ITM Component Identification Register #0

__I uint32_t ITM_Type::CID1

Offset: ITM Component Identification Register #1

__I uint32_t ITM_Type::CID2

Offset: ITM Component Identification Register #2

__I uint32_t ITM_Type::CID3

Offset: ITM Component Identification Register #3

__IO uint32_t ITM_Type::IMCR

Offset: ITM Integration Mode Control Register

__IO uint32_t ITM_Type::IRR

Offset: ITM Integration Read Register

__IO uint32_t ITM_Type::IWR

Offset: ITM Integration Write Register

__IO uint32_t ITM_Type::LAR

Offset: ITM Lock Access Register

__IO uint32_t ITM_Type::LSR

Offset: ITM Lock Status Register

__I uint32_t ITM_Type::PID0

Offset: ITM Peripheral Identification Register #0

__I uint32_t ITM_Type::PID1

Offset: ITM Peripheral Identification Register #1

__I uint32_t ITM_Type::PID2

Offset: ITM Peripheral Identification Register #2

__I uint32_t ITM_Type::PID3

Offset: ITM Peripheral Identification Register #3

__I uint32_t ITM_Type::PID4

Offset: ITM Peripheral Identification Register #4

__I uint32_t ITM_Type::PID5

Offset: ITM Peripheral Identification Register #5

__I uint32_t ITM_Type::PID6

Offset: ITM Peripheral Identification Register #6

__I uint32_t ITM_Type::PID7

Offset: ITM Peripheral Identification Register #7

__O { ... } ITM_Type::PORT[32]

Offset: 0x00 ITM Stimulus Port Registers

uint32_t ITM_Type::RESERVED0[864]

uint32_t ITM_Type::RESERVED1[15]

uint32_t ITM_Type::RESERVED2[15]

uint32_t ITM_Type::RESERVED3[29]

uint32_t ITM_Type::RESERVED4[43]

uint32_t ITM_Type::RESERVED5[6]

__IO uint32_t ITM_Type::TCR

Offset: ITM Trace Control Register

__IO uint32_t ITM_Type::TER

Offset: ITM Trace Enable Register

__IO uint32_t ITM_Type::TPR

Offset: ITM Trace Privilege Register

__O uint16_t ITM_Type::u16

Offset: ITM Stimulus Port 16-bit

__O uint32_t ITM_Type::u32

Offset: ITM Stimulus Port 32-bit

__O uint8_t ITM_Type::u8

Offset: ITM Stimulus Port 8-bit

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The documentation for this struct was generated from the following file:

• /var/www/html/SJSU-DEV-Linux/firmware/default/lib/L0_LowLevel/core_cm3.h