|
Data Structures | |
| struct | ITM_Type |
Macros | |
| #define | ITM_TPR_PRIVMASK_Pos 0 |
| #define | ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) |
| #define | ITM_TCR_BUSY_Pos 23 |
| #define | ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) |
| #define | ITM_TCR_ATBID_Pos 16 |
| #define | ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) |
| #define | ITM_TCR_TSPrescale_Pos 8 |
| #define | ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) |
| #define | ITM_TCR_SWOENA_Pos 4 |
| #define | ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) |
| #define | ITM_TCR_DWTENA_Pos 3 |
| #define | ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) |
| #define | ITM_TCR_SYNCENA_Pos 2 |
| #define | ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) |
| #define | ITM_TCR_TSENA_Pos 1 |
| #define | ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) |
| #define | ITM_TCR_ITMENA_Pos 0 |
| #define | ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) |
| #define | ITM_IWR_ATVALIDM_Pos 0 |
| #define | ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) |
| #define | ITM_IRR_ATREADYM_Pos 0 |
| #define | ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) |
| #define | ITM_IMCR_INTEGRATION_Pos 0 |
| #define | ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) |
| #define | ITM_LSR_ByteAcc_Pos 2 |
| #define | ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) |
| #define | ITM_LSR_Access_Pos 1 |
| #define | ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) |
| #define | ITM_LSR_Present_Pos 0 |
| #define | ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) |
Detailed Description
memory mapped structure for Instrumentation Trace Macrocell (ITM)
Macro Definition Documentation
| #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Pos 0 |
ITM IMCR: INTEGRATION Position
| #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Pos 0 |
ITM IRR: ATREADYM Position
| #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Pos 0 |
ITM IWR: ATVALIDM Position
| #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Pos 1 |
ITM LSR: Access Position
| #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Pos 2 |
ITM LSR: ByteAcc Position
| #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Pos 0 |
ITM LSR: Present Position
| #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_ATBID_Pos 16 |
ITM TCR: ATBID Position
| #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Pos 23 |
ITM TCR: BUSY Position
| #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Pos 3 |
ITM TCR: DWTENA Position
| #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Pos 0 |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Pos 4 |
ITM TCR: SWOENA Position
| #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Pos 2 |
ITM TCR: SYNCENA Position
| #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Pos 1 |
ITM TCR: TSENA Position
| #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
| #define ITM_TCR_TSPrescale_Pos 8 |
ITM TCR: TSPrescale Position
| #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Pos 0 |
ITM TPR: PRIVMASK Position
