NVIC_Type Struct Reference

#include <core_cm3.h>

Data Fields
__IO uint32_t	ISER [8]
uint32_t	RESERVED0 [24]
__IO uint32_t	ICER [8]
uint32_t	RSERVED1 [24]
__IO uint32_t	ISPR [8]
uint32_t	RESERVED2 [24]
__IO uint32_t	ICPR [8]
uint32_t	RESERVED3 [24]
__IO uint32_t	IABR [8]
uint32_t	RESERVED4 [56]
__IO uint8_t	IP [240]
uint32_t	RESERVED5 [644]
__O uint32_t	STIR

Field Documentation

__IO uint32_t NVIC_Type::IABR[8]

Offset: 0x200 Interrupt Active bit Register

__IO uint32_t NVIC_Type::ICER[8]

Offset: 0x080 Interrupt Clear Enable Register

__IO uint32_t NVIC_Type::ICPR[8]

Offset: 0x180 Interrupt Clear Pending Register

__IO uint8_t NVIC_Type::IP[240]

Offset: 0x300 Interrupt Priority Register (8Bit wide)

__IO uint32_t NVIC_Type::ISER[8]

Offset: 0x000 Interrupt Set Enable Register

__IO uint32_t NVIC_Type::ISPR[8]

Offset: 0x100 Interrupt Set Pending Register

uint32_t NVIC_Type::RESERVED0[24]

uint32_t NVIC_Type::RESERVED2[24]

uint32_t NVIC_Type::RESERVED3[24]

uint32_t NVIC_Type::RESERVED4[56]

uint32_t NVIC_Type::RESERVED5[644]

uint32_t NVIC_Type::RSERVED1[24]

__O uint32_t NVIC_Type::STIR

Offset: 0xE00 Software Trigger Interrupt Register

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The documentation for this struct was generated from the following file:

• /var/www/html/SJSU-DEV-Linux/firmware/default/lib/L0_LowLevel/core_cm3.h