SCB_Type Struct Reference

#include <core_cm3.h>

Data Fields
__I uint32_t	CPUID
__IO uint32_t	ICSR
__IO uint32_t	VTOR
__IO uint32_t	AIRCR
__IO uint32_t	SCR
__IO uint32_t	CCR
__IO uint8_t	SHP [12]
__IO uint32_t	SHCSR
__IO uint32_t	CFSR
__IO uint32_t	HFSR
__IO uint32_t	DFSR
__IO uint32_t	MMFAR
__IO uint32_t	BFAR
__IO uint32_t	AFSR
__I uint32_t	PFR [2]
__I uint32_t	DFR
__I uint32_t	ADR
__I uint32_t	MMFR [4]
__I uint32_t	ISAR [5]

Field Documentation

__I uint32_t SCB_Type::ADR

Offset: 0x4C Auxiliary Feature Register

__IO uint32_t SCB_Type::AFSR

Offset: 0x3C Auxiliary Fault Status Register

__IO uint32_t SCB_Type::AIRCR

Offset: 0x0C Application Interrupt / Reset Control Register

__IO uint32_t SCB_Type::BFAR

Offset: 0x38 Bus Fault Address Register

__IO uint32_t SCB_Type::CCR

Offset: 0x14 Configuration Control Register

__IO uint32_t SCB_Type::CFSR

Offset: 0x28 Configurable Fault Status Register

__I uint32_t SCB_Type::CPUID

Offset: 0x00 CPU ID Base Register

__I uint32_t SCB_Type::DFR

Offset: 0x48 Debug Feature Register

__IO uint32_t SCB_Type::DFSR

Offset: 0x30 Debug Fault Status Register

__IO uint32_t SCB_Type::HFSR

Offset: 0x2C Hard Fault Status Register

__IO uint32_t SCB_Type::ICSR

Offset: 0x04 Interrupt Control State Register

__I uint32_t SCB_Type::ISAR[5]

Offset: 0x60 ISA Feature Register

__IO uint32_t SCB_Type::MMFAR

Offset: 0x34 Mem Manage Address Register

__I uint32_t SCB_Type::MMFR[4]

Offset: 0x50 Memory Model Feature Register

__I uint32_t SCB_Type::PFR[2]

Offset: 0x40 Processor Feature Register

__IO uint32_t SCB_Type::SCR

Offset: 0x10 System Control Register

__IO uint32_t SCB_Type::SHCSR

Offset: 0x24 System Handler Control and State Register

__IO uint8_t SCB_Type::SHP[12]

Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15)

__IO uint32_t SCB_Type::VTOR

Offset: 0x08 Vector Table Offset Register

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The documentation for this struct was generated from the following file:

• /var/www/html/SJSU-DEV-Linux/firmware/default/lib/L0_LowLevel/core_cm3.h