spi_dma.c File Reference

#include "LPC17xx.h"

Include dependency graph for spi_dma.c:

Macros
#define	SPI_DMA_TX_NUM   0
	DMA Channel number for SSP Tx. More...
#define	SPI_DMA_RX_NUM   1
	DMA Channel number for SSP Rx. More...
#define	SSP1_TX_CHAN   2UL
	DMA source for TX of SSP1. More...
#define	SSP1_RX_CHAN   3UL
	DMA source for RX of SSP1. More...
#define	SRC_INCR_BIT   (1 << 26)
#define	DST_INCR_BIT   (1 << 27)
#define	TCIE_BIT   (1 << 31)
#define	SRC_BURST_4_BYTES   (1 << 12)
#define	DST_BURST_4_BYTES   (1 << 15)
#define	SRC_WIDTH_2_BYTES   (1 << 18)
#define	DST_WIDTH_2_BYTES   (1 << 21)
#define	M_TO_P_BIT   (1 << 11)
#define	P_TO_M_BIT   (2 << 11)
#define	ER_INTR_BIT   (1 << 14)
#define	TC_INTR_BIT   (1 << 15)

Enumerations
enum	{ err_Dma = 0, err_Len = 1, err_busy = 2, err_spiFifo = 3 }

Functions
void	ssp1_dma_init ()
unsigned	ssp1_dma_transfer_block (unsigned char *pBuffer, uint32_t num_bytes, char is_write_op)

Macro Definition Documentation

#define DST_BURST_4_BYTES   (1 << 15)

#define DST_INCR_BIT   (1 << 27)

#define DST_WIDTH_2_BYTES   (1 << 21)

#define ER_INTR_BIT   (1 << 14)

#define M_TO_P_BIT   (1 << 11)

#define P_TO_M_BIT   (2 << 11)

#define SPI_DMA_RX_NUM   1

DMA Channel number for SSP Rx.

#define SPI_DMA_TX_NUM   0

DMA Channel number for SSP Tx.

#define SRC_BURST_4_BYTES   (1 << 12)

#define SRC_INCR_BIT   (1 << 26)

#define SRC_WIDTH_2_BYTES   (1 << 18)

#define SSP1_RX_CHAN   3UL

DMA source for RX of SSP1.

#define SSP1_TX_CHAN   2UL

DMA source for TX of SSP1.

#define TC_INTR_BIT   (1 << 15)

#define TCIE_BIT   (1 << 31)

Enumeration Type Documentation

anonymous enum

Enumerator
err_Dma
err_Len
err_busy
err_spiFifo

Function Documentation

void ssp1_dma_init

(

)

unsigned ssp1_dma_transfer_block	(	unsigned char *	pBuffer,
		uint32_t	num_bytes,
		char	is_write_op
	)

Transfers data over SPI (SSP#1)

Parameters

pBuffer	The read or write buffer
num_bytes	The length of the transfer in bytes
is_write_op	Non-zero for Write-operation, zero for read operation

Note

If is_write_op is true:

• SPI data is sent from pBuffer
• SPI data is copied from SSP DR to dummy buffer and discarded If is_write_op is false (read operation) :
• SPI data is copied from SSP DR to pBuffer
• 0xFF is sent out for each byte transfered

Returns

0 upon success, or non-zero upon failure.

TO DO : Optimize SSP1 DMA

• Try setting source and destination burst size to 4
• Try setting 16-bit SPI, and source and destination width to 1 WORD

LPC_SSP1->CR0 : B3:B0. 0b0111 = 8-bit and 0b1111 = 16-bit LPC_SSP1->CR0 |= (1<<3); // 16-bit LPC_SSP1->CR0 &= ~(1<<3); // 8-bit

Bits of DMACCControl: Transfer size: B11:B0 Source Burst Size: B14:B12 - 0:1, 1:4, 2:8, 3:16 bytes Dest. Burst Size: B17:B15 - 0:1, 1:4, 2:8, 3:16 bytes Source Width: B20:B18 - 0:Byte, 1:Word, 2:DWORD Dest. Width: B23:B21 - 0:Byte, 1:Word, 2:DWORD Source increment: B26 Destination increment: B27 Terminal count interrupt enable: B31

Bits of DMACCConfig: Enable: B0 Source Peripheral: B5:B1 (ignored if source is memory) Dest. Peripheral: B10:B6 (ignored if dest. is memory) Transfer type: B13:B11 - See below Interrupt Error Mask: B14 Terminal Count Interrupt : B15

Bits for transfer type: 000 - Memory to Memory 001 - Memory to Peripheral 010 - Peripheral to Memory 011 - Source peripheral to destination peripheral

Clear existing terminal count and error interrupts otherwise DMA will not start.

From SPI to buffer: For write operation :

• Receive data into dummy buffer
• Don't increment destination For read operation:
• Read data into pBuffer
• Increment destination

From buffer to SPI : For write operation :

• Source data is pBuffer
• Increment source data For read operation:
• Source data is buffer with 0xFF
• Don't increment source data

Channel must be fully configured and then enabled separately. Setting DMACR's Rx/Tx bits should trigger the DMA