trcHardwarePort.h
Go to the documentation of this file.
1 /*******************************************************************************
2  * Tracealyzer v3.0.2 Recorder Library
3  * Percepio AB, www.percepio.com
4  *
5  * trcHardwarePort.h
6  *
7  * Contains together with trcHardwarePort.c all hardware portability issues of
8  * the trace recorder library.
9  *
10  * Terms of Use
11  * This software is copyright Percepio AB. The recorder library is free for
12  * use together with Percepio products. You may distribute the recorder library
13  * in its original form, including modifications in trcPort.c and trcPort.h
14  * given that these modification are clearly marked as your own modifications
15  * and documented in the initial comment section of these source files.
16  * This software is the intellectual property of Percepio AB and may not be
17  * sold or in other ways commercially redistributed without explicit written
18  * permission by Percepio AB.
19  *
20  * Disclaimer
21  * The trace tool and recorder library is being delivered to you AS IS and
22  * Percepio AB makes no warranty as to its use or performance. Percepio AB does
23  * not and cannot warrant the performance or results you may obtain by using the
24  * software or documentation. Percepio AB make no warranties, express or
25  * implied, as to noninfringement of third party rights, merchantability, or
26  * fitness for any particular purpose. In no event will Percepio AB, its
27  * technology partners, or distributors be liable to you for any consequential,
28  * incidental or special damages, including any lost profits or lost savings,
29  * even if a representative of Percepio AB has been advised of the possibility
30  * of such damages, or for any claim by any third party. Some jurisdictions do
31  * not allow the exclusion or limitation of incidental, consequential or special
32  * damages, or the exclusion of implied warranties or limitations on how long an
33  * implied warranty may last, so the above limitations may not apply to you.
34  *
35  * Tabs are used for indent in this file (1 tab = 4 spaces)
36  *
37  * Copyright Percepio AB, 2014.
38  * www.percepio.com
39  ******************************************************************************/
40 
41 #ifndef TRCPORT_H
42 #define TRCPORT_H
43 #include <stdint.h>
44 
45 /* If Win32 port */
46 #ifdef WIN32
47 
48  #undef _WIN32_WINNT
49  #define _WIN32_WINNT 0x0600
50 
51  /* Standard includes. */
52  #include <stdio.h>
53  #include <windows.h>
54  #include <direct.h>
55 
56 /*******************************************************************************
57  * The Win32 port by default saves the trace to file and then kills the
58  * program when the recorder is stopped, to facilitate quick, simple tests
59  * of the recorder.
60  ******************************************************************************/
61  #define WIN32_PORT_SAVE_WHEN_STOPPED 1
62  #define WIN32_PORT_EXIT_WHEN_STOPPED 1
63 
64 #endif
65 
66 #define DIRECTION_INCREMENTING 1
67 #define DIRECTION_DECREMENTING 2
68 
69 /******************************************************************************
70  * Supported ports
71  *
72  * PORT_HWIndependent
73  * A hardware independent fallback option for event timestamping. Provides low
74  * resolution timestamps based on the OS tick.
75  * This may be used on the Win32 port, but may also be used on embedded hardware
76  * platforms. All time durations will be truncated to the OS tick frequency,
77  * typically 1 KHz. This means that a task or ISR that executes in less than
78  * 1 ms get an execution time of zero.
79  *
80  * PORT_APPLICATION_DEFINED
81  * Allows for defining the port macros in other source code files.
82  *
83  * PORT_Win32
84  * "Accurate" timestamping based on the Windows performance counter for Win32
85  * builds. Note that this gives the host machine time, not the kernel time.
86  *
87  * Hardware specific ports
88  * To get accurate timestamping, a hardware timer is necessary. Below are the
89  * available ports. Some of these are "unofficial", meaning that
90  * they have not yet been verified by Percepio but have been contributed by
91  * external developers. They should work, otherwise let us know by emailing
92  * support@percepio.com. Some work on any OS platform, while other are specific
93  * to a certain operating system.
94  *****************************************************************************/
95 
96 /****** Port Name ********************** Code ***** Official ** OS Platform *********/
97 #define PORT_APPLICATION_DEFINED -2 /* - - */
98 #define PORT_NOT_SET -1 /* - - */
99 #define PORT_HWIndependent 0 /* Yes Any */
100 #define PORT_Win32 1 /* Yes FreeRTOS on Win32 */
101 #define PORT_Atmel_AT91SAM7 2 /* No Any */
102 #define PORT_Atmel_UC3A0 3 /* No Any */
103 #define PORT_ARM_CortexM 4 /* Yes Any */
104 #define PORT_Renesas_RX600 5 /* Yes Any */
105 #define PORT_Microchip_dsPIC_AND_PIC24 6 /* Yes Any */
106 #define PORT_TEXAS_INSTRUMENTS_TMS570 7 /* No Any */
107 #define PORT_TEXAS_INSTRUMENTS_MSP430 8 /* No Any */
108 #define PORT_MICROCHIP_PIC32MX 9 /* Yes Any */
109 #define PORT_XILINX_PPC405 10 /* No FreeRTOS */
110 #define PORT_XILINX_PPC440 11 /* No FreeRTOS */
111 #define PORT_XILINX_MICROBLAZE 12 /* No Any */
112 #define PORT_NXP_LPC210X 13 /* No Any */
113 #define PORT_MICROCHIP_PIC32MZ 14 /* Yes Any */
114 #define PORT_ARM_CORTEX_A9 15 /* No Any */
115 #define PORT_ARM_CORTEX_M0 16 /* Yes Any */
116 
117 #include "trcConfig.h"
118 
119 /*******************************************************************************
120  * IRQ_PRIORITY_ORDER
121  *
122  * Macro which should be defined as an integer of 0 or 1.
123  *
124  * This should be 0 if lower IRQ priority values implies higher priority
125  * levels, such as on ARM Cortex M. If the opposite scheme is used, i.e.,
126  * if higher IRQ priority values means higher priority, this should be 1.
127  *
128  * This setting is not critical. It is used only to sort and colorize the
129  * interrupts in priority order, in case you record interrupts using
130  * the vTraceStoreISRBegin and vTraceStoreISREnd routines.
131  *
132  ******************************************************************************
133  *
134  * HWTC Macros
135  *
136  * These four HWTC macros provides a hardware isolation layer representing a
137  * generic hardware timer/counter used for driving the operating system tick,
138  * such as the SysTick feature of ARM Cortex M3/M4, or the PIT of the Atmel
139  * AT91SAM7X.
140  *
141  * HWTC_COUNT: The current value of the counter. This is expected to be reset
142  * a each tick interrupt. Thus, when the tick handler starts, the counter has
143  * already wrapped.
144  *
145  * HWTC_COUNT_DIRECTION: Should be one of:
146  * - DIRECTION_INCREMENTING - for hardware timer/counters of incrementing type
147  * such as the PIT on Atmel AT91SAM7X.
148  * When the counter value reach HWTC_PERIOD, it is reset to zero and the
149  * interrupt is signaled.
150  * - DIRECTION_DECREMENTING - for hardware timer/counters of decrementing type
151  * such as the SysTick on ARM Cortex M3/M4 chips.
152  * When the counter value reach 0, it is reset to HWTC_PERIOD and the
153  * interrupt is signaled.
154  *
155  * HWTC_PERIOD: The number of increments or decrements of HWTC_COUNT between
156  * two OS tick interrupts. This should preferably be mapped to the reload
157  * register of the hardware timer, to make it more portable between chips in the
158  * same family. The macro should in most cases be (reload register + 1).
159  * For FreeRTOS, this can in most cases be defined as
160  * #define HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ)
161  *
162  * HWTC_DIVISOR: If the timer frequency is very high, like on the Cortex M chips
163  * (where the SysTick runs at the core clock frequency), the "differential
164  * timestamping" used in the recorder will more frequently insert extra XTS
165  * events to store the timestamps, which increases the event buffer usage.
166  * In such cases, to reduce the number of XTS events and thereby get longer
167  * traces, you use HWTC_DIVISOR to scale down the timestamps and frequency.
168  * Assuming a OS tick rate of 1 KHz, it is suggested to keep the effective timer
169  * frequency below 65 MHz to avoid an excessive amount of XTS events. Thus, a
170  * Cortex M chip running at 72 MHZ should use a HWTC_DIVISOR of 2, while a
171  * faster chip require a higher HWTC_DIVISOR value.
172  *
173  * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
174  * or the trace recorder library. Typically you should not need to change
175  * the code of vTracePortGetTimeStamp if using the HWTC macros.
176  *
177  ******************************************************************************/
178 
179 #if (SELECTED_PORT == PORT_Win32)
180  // This can be used as a template for any free-running 32-bit counter
181  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
182  #define HWTC_COUNT (ulGetRunTimeCounterValue())
183  #define HWTC_PERIOD 0
184  #define HWTC_DIVISOR 1
185 
186  // Please update according to your system...
187  #define IRQ_PRIORITY_ORDER 1
188 
189 #elif (SELECTED_PORT == PORT_HWIndependent)
190  // OS Tick only (typically 1 ms resolution)
191  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
192  #define HWTC_COUNT 0
193  #define HWTC_PERIOD 1
194  #define HWTC_DIVISOR 1
195 
196  // Please update according to your system...
197  #define IRQ_PRIORITY_ORDER NOT_SET
198 
199 
200 #elif (SELECTED_PORT == PORT_ARM_CortexM)
201 
202  void prvTraceInitCortexM(void);
203 
204  #define REG_DEMCR (*(volatile unsigned int*)0xE000EDFC)
205  #define REG_DWT_CTRL (*(volatile unsigned int*)0xE0001000)
206  #define REG_DWT_CYCCNT (*(volatile unsigned int*)0xE0001004)
207  #define REG_DWT_EXCCNT (*(volatile unsigned int*)0xE000100C)
208 
209  /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */
210  #define DEMCR_TRCENA (1 << 24)
211 
212  /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */
213  #define DWT_CTRL_NOPRFCNT (1 << 24)
214 
215  /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */
216  #define DWT_CTRL_NOCYCCNT (1 << 25)
217 
218  /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */
219  #define DWT_CTRL_EXCEVTENA (1 << 18)
220 
221  /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */
222  #define DWT_CTRL_CYCCNTENA (1)
223 
224  #define PORT_SPECIFIC_INIT() prvTraceInitCortexM()
225 
226  extern uint32_t DWT_CYCLES_ADDED;
227 
228  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
229  #define HWTC_COUNT (REG_DWT_CYCCNT + DWT_CYCLES_ADDED)
230  #define HWTC_PERIOD 0
231  #define HWTC_DIVISOR 4
232 
233  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
234 
235 #elif (SELECTED_PORT == PORT_ARM_CORTEX_M0)
236  #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
237  #define HWTC_COUNT (*((uint32_t*)0xE000E018))
238  #define HWTC_PERIOD ((*(uint32_t*)0xE000E014) + 1)
239  #define HWTC_DIVISOR 48
240 
241  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
242 
243 #elif (SELECTED_PORT == PORT_Renesas_RX600)
244 
245  #include "iodefine.h"
246 
247  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
248  #define HWTC_COUNT (CMT0.CMCNT)
249  #define HWTC_PERIOD (CMT0.CMCOR + 1)
250  #define HWTC_DIVISOR 1
251  #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
252 
253 #elif ((SELECTED_PORT == PORT_MICROCHIP_PIC32MX) || (SELECTED_PORT == PORT_MICROCHIP_PIC32MZ))
254 
255  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
256  #define HWTC_COUNT (TMR1)
257  #define HWTC_PERIOD (PR1 + 1)
258  #define HWTC_DIVISOR 1
259  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
260 
261 #elif (SELECTED_PORT == PORT_Microchip_dsPIC_AND_PIC24)
262 
263  /* For Microchip PIC24 and dsPIC (16 bit) */
264 
265  /* Note: The trace library is designed for 32-bit MCUs and is slower than
266  intended on 16-bit MCUs. Storing an event on a PIC24 takes about 70 usec.
267  In comparison, this is 10-20 times faster on a 32-bit MCU... */
268 
269  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
270  #define HWTC_COUNT (TMR1)
271  #define HWTC_PERIOD (PR1+1)
272  #define HWTC_DIVISOR 1
273  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
274 
275 #elif (SELECTED_PORT == PORT_Atmel_AT91SAM7)
276 
277  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
278 
279  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
280  #define HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
281  #define HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
282  #define HWTC_DIVISOR 1
283  #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
284 
285 #elif (SELECTED_PORT == PORT_Atmel_UC3A0)
286 
287  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
288  /* For Atmel AVR32 (AT32UC3A).*/
289 
290  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
291  #define HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
292  #define HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
293  #define HWTC_DIVISOR 1
294  #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
295 
296 #elif (SELECTED_PORT == PORT_NXP_LPC210X)
297 
298  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
299  /* Tested with LPC2106, but should work with most LPC21XX chips. */
300 
301  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
302  #define HWTC_COUNT *((uint32_t *)0xE0004008 )
303  #define HWTC_PERIOD *((uint32_t *)0xE0004018 )
304  #define HWTC_DIVISOR 1
305  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
306 
307 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_TMS570)
308 
309  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
310 
311  #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
312  #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
313  #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
314  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
315  #define HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
316  #define HWTC_PERIOD (RTIUDCP0)
317  #define HWTC_DIVISOR 1
318 
319  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
320 
321 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_MSP430)
322 
323  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
324 
325  #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
326  #define HWTC_COUNT (TA0R)
327  #define HWTC_PERIOD (((uint16_t)TACCR0)+1)
328  #define HWTC_DIVISOR 1
329  #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
330 
331 #elif (SELECTED_PORT == PORT_XILINX_PPC405)
332 
333  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
334 
335  #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
336  #define HWTC_COUNT mfspr(0x3db)
337  #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
338  /* For FreeRTOS only - found no generic OS independent solution for the PPC405 architecture. */
339  #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC405
340  #else
341  /* Not defined for other operating systems yet */
342  #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
343  #endif
344  #define HWTC_DIVISOR 1
345  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
346 
347 #elif (SELECTED_PORT == PORT_XILINX_PPC440)
348 
349  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
350  /* This should work with most PowerPC chips */
351 
352  #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
353  #define HWTC_COUNT mfspr(0x016)
354  #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
355  /* For FreeRTOS only - found no generic OS independent solution for the PPC440 architecture. */
356  #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC440
357  #else
358  /* Not defined for other operating systems yet */
359  #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
360  #endif
361  #define HWTC_DIVISOR 1
362  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
363 
364 #elif (SELECTED_PORT == PORT_XILINX_MICROBLAZE)
365 
366  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
367 
368  /* This should work with most Microblaze configurations.
369  * It uses the AXI Timer 0 - the tick interrupt source.
370  * If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.
371  */
372  #include "xtmrctr_l.h"
373 
374  #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
375  #define HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
376  #define HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
377  #define HWTC_DIVISOR 16
378  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
379 
380 #elif (SELECTED_PORT == PORT_ARM_CORTEX_A9)
381 
382  /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
383 
384  #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
385  #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
386 
387  #define CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(0xF8F00600 + 0))
388  #define CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(0xF8F00600 + 4))
389  #define CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(0xF8F00600 + 8))
390 
391  #define CA9_MPCORE_PRIVCTR_PRESCALER (((CA9_MPCORE_PRIVCTR_CONTROL_REG & CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
392 
393 
394  #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
395  #define HWTC_COUNT CA9_MPCORE_PRIVCTR_COUNTER_REG
396  #define HWTC_PERIOD ((CA9_MPCORE_PRIVCTR_PERIOD_REG * CA9_MPCORE_PRIVCTR_PRESCALER) + 1)
397 
398  //NOTE: The private timer ticks with a very high frequency (half the core-clock usually),
399  //but offers the possibility to apply a prescaler. Depending on the prescaler you set the
400  //HWTC_DIVISOR may need to be raised. Refer to the notes at the beginning of this file
401  //for more information.
402  #define HWTC_DIVISOR 1
403 
404  #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
405 
406 #elif (SELECTED_PORT == PORT_APPLICATION_DEFINED)
407 
408  #if !( defined (HWTC_COUNT_DIRECTION) && defined (HWTC_COUNT) && defined (HWTC_PERIOD) && defined (HWTC_DIVISOR) && defined (IRQ_PRIORITY_ORDER) )
409  #error SELECTED_PORT is PORT_APPLICATION_DEFINED but not all of the necessary constants have been defined.
410  #endif
411 
412 #elif (SELECTED_PORT != PORT_NOT_SET)
413 
414  #error "SELECTED_PORT had unsupported value!"
415  #define SELECTED_PORT PORT_NOT_SET
416 
417 #endif
418 
419 #if (SELECTED_PORT != PORT_NOT_SET)
420 
421  #ifndef HWTC_COUNT_DIRECTION
422  #error "HWTC_COUNT_DIRECTION is not set!"
423  #endif
424 
425  #ifndef HWTC_COUNT
426  #error "HWTC_COUNT is not set!"
427  #endif
428 
429  #ifndef HWTC_PERIOD
430  #error "HWTC_PERIOD is not set!"
431  #endif
432 
433  #ifndef HWTC_DIVISOR
434  #error "HWTC_DIVISOR is not set!"
435  #endif
436 
437  #ifndef IRQ_PRIORITY_ORDER
438  #error "IRQ_PRIORITY_ORDER is not set!"
439  #elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
440  #error "IRQ_PRIORITY_ORDER has bad value!"
441  #endif
442 
443  #if (HWTC_DIVISOR < 1)
444  #error "HWTC_DIVISOR must be a non-zero positive value!"
445  #endif
446 
447 #endif
448 /*******************************************************************************
449  * vTraceConsoleMessage
450  *
451  * A wrapper for your system-specific console "printf" console output function.
452  * This needs to be correctly defined to see status reports from the trace
453  * status monitor task (this is defined in trcUser.c).
454  ******************************************************************************/
455 #define vTraceConsoleMessage(x)
456 
457 /*******************************************************************************
458  * vTracePortGetTimeStamp
459  *
460  * Returns the current time based on the HWTC macros which provide a hardware
461  * isolation layer towards the hardware timer/counter.
462  *
463  * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
464  * or the trace recorder library. Typically you should not need to change
465  * the code of vTracePortGetTimeStamp if using the HWTC macros.
466  *
467  ******************************************************************************/
468 void vTracePortGetTimeStamp(uint32_t *puiTimestamp);
469 
470 #endif
void vTracePortGetTimeStamp(uint32_t *puiTimestamp)